1. Field of the Invention
The present invention relates to semiconductor devices, and in particular, relates to a semiconductor device having a plurality of bonding pads as bonding option and a test circuit, the bonding pads being connected to common internal circuits, the test circuit testing the states of interconnects between the bonding pads and the internal circuits, respectively.
2. Description of the Related Art
Recently, digital consumer devices have become smaller. Particularly, mobile devices are significantly reduced in size because a plurality of semiconductor chips are mounted on a single substrate of each device. For example, a plurality of chips, e.g., a CPU and memory devices such as a DRAM and a flash memory, are mounted on one substrate and are packaged with a resin, thus forming a single device component. Packaging technology includes various packaging designs, such as Multi-chip Package, System In Package, and Package On Package.
Packaging is principally performed in a factory of each device manufacturer. Therefore, the device manufacturer purchases semiconductor chips, such as CPUs and DRAMs, from individual semiconductor manufacturers. Each device manufacturer designs a device including the chips as compact as possible. Accordingly, the arrangement of bonding pads needed for each semiconductor chip varies from device manufacturer to device manufacturer, or from device to device. Consequently, each semiconductor manufacturer has to provide semiconductor chips with various bonding-pad arrangements in response to requests of the respective device manufacturers. For instance, a device manufacturer A requests DRAMs each having an array of pads on the left part of the chip and another device manufacturer B requests DRAMs each having an array of pads on the right part of the chip.
Under the above-described circumstances, the semiconductor manufacturers for the production of DRAMs have to produce chips with various pad arrangements for individual device manufacturers and deliver the chips to the respective manufacturers. Unfortunately, the production and delivery of the chips with various pad arrangements need time and money, leading to burdens on the semiconductor manufacturers. In consideration of the circumstances, the semiconductor manufacturers each provide the same semiconductor chips, e.g., DRAM chips each having a plurality of pads thereon in order to respond to all of requests of device manufacturers. Each device manufacturer selects any group of pads and performs a bonding process on the selected pads. Accordingly, the same DRAM chips can be delivered to the respective device manufacturers. Providing a plurality of pads, selecting necessary pads from the pads, and bonding the selected pads are called a bonding option technique.
However, since each chip includes a plurality of pads connected to common internal circuits, the semiconductor manufacturers have another problem related to an operation test. Before the shipment of chips to the respective device manufacturers as clients, each chip has to be subjected to an electrical characteristics test. If each chip includes pad groups as bonding option, any of the groups has to be selected for each client and be tested. Disadvantageously, selecting pads desired by the client from the pads, setting a probe card for bringing probes, corresponding to pads to be tested, into contact with the pads on the chip, and testing the pads also lead to a waste of time and money.
Accordingly, one group of pads are subjected to a test for DRAM, thus checking internal functions of each DRAM. In this case, other pads and interconnects are not checked. It is, therefore, necessary to test the unchecked pads and interconnects. It is preferred that unchecked pads is tested by simple, low-cost means without using a probe card.
Japanese Unexamined Patent Application Publication No. 2003-132698 discloses a test circuit for performing an operation test on semiconductor devices. In this test circuit, a plurality of memories are simultaneously subjected to the read operation to thereby detect a defective memory. The test circuit includes a current detection circuit and a fault-location identification circuit. The current detection circuit detects current flowing through an output driver of a memory connected to a tri-state bus. If a memory output includes an error, a shoot-through current flows. This shoot-through current is detected so as to identify a defective memory. For example, if an interconnect is disconnected, the disconnection cannot be detected because the test circuit detects different output levels. Unfortunately, this circuit cannot be applied to a test for interconnects connected to untested pads on a semiconductor device having a plurality of pads.
As described above, in a semiconductor device having a plurality of bonding pads connected to common internal circuits, some of the bonding pads and the corresponding interconnects are subjected to the operation test but the other pads and the associated interconnects in the vicinities thereof are untested. In the following description, a bonding pad and the associated interconnect in the vicinity thereof will be abbreviated to “pad interconnect”. It is preferred to provide a method for readily testing unchecked pad interconnects without bring a probe card into contact with the unchecked pads.